FinFET Technology and Challenges



 

Speaker : Jeffrey Gambino (IBM)
Course Duration : 2 days Time & Date : 27th – 28th Aug 2015
Course Venue : M Hotel, Singapore
Course Fee : SGD 800 per Participant (Singaporean & PR)
                          SGD 1,100 per Participant (Foreigner)

 FinFET Technology and Challenges  

Course Overview

FinFET transistor architecture is fast becoming the technology of choice at feature sizes below 20nm. The FinFET Technology and Challenges course will explain FinFET technology and its semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline. Participants learn basic but powerful aspects about FinFET technology. This skill-building series is divided into three segments:
1.FinFET Device Physics Overview. Participants study the device physics associated with the FinFET. They learn why the FinFET has better channel control and how that translates into better performance than a planar FET.
2.FinFET Manufacturing Overview. Participants learn how semiconductor manufacturers are currently processing FinFET devices and the difficulties associated with three-dimensional structures from a processing and metrology standpoint.
3.FinFET Reliability. They also study the failure mechanisms and techniques used for studying the reliability of these devices.

 


Course Outline

1. Device Physics

   1.1. Planar FET characteristics
   1.2. FinFET characteristics
   1.3. Performance comparisons

2. FinFET Manufacturing Overview

   2.1. Substrates
     2.1.1. Bulk
     2.1.2. SOI

2.2. FinFET Types

   2.3. Process Sequence
   2.4. Processing Issues
     2.4.1. Lithography
     2.4.2. Etch
     2.4.3. Metrology

3. FinFET Reliability

   3.1. Defect density issues
   3.2. Gate Stack
   3.3. Transistor Reliability
        (BTI and Hot Carriers)
   3.4. Heat dissipation issues
   3.5. Failure analysis challenges

4. Future Directions for FinFETs

   4.1. Comparison of FD-SOI and FinFETs
        – Are FinFETs a better choice?
   4.2.Scaling

Trainer bio data

Dr. Jeffrey Gambino

jeffrey.gambino

Senior technical staff at International Business Machines (IBM Microelectronics); CMOS integration at IBM Semiconductor Research and Development Center. In the past 30 year +, he has been involved in the Researh and Development of RF technology, DRAM, On-chip interconnect technology, CMOS image sensor, Chip-package interaction, Through-silicon vias and other latest technologies.

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15- mm DRAM products. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.


To Register

Course Administrator:
Mr. Chan Choonkit, +65 97638510,
email: choonkit@wintech-nano.com

 

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